Anritsu MP1777A Spezifikationen Seite 25

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http://www.anritsu.com 153
DIGITAL LINK MEASURING INSTRUMENTS
2
1: Mounted MP0122A/B, 2: Mounted MP0121A
52/156/622/2488/9953M (SDH)
Bit rate 51.84, 155.52, 622.08, 2488.32, 9953.28 Mbit/s
52M (electrical: B3ZS)
1
: ANSI T1.102, 0/450 ft
52M (optical): As per MP0122B unit optical interface specifications
156M (electrical: CMI)
2
: ITU-T G.703
Level/waveform 156M (optical): As per optical 156M/622M unit specifications
622M (electrical/optical): As per optical 156M/622M unit and NRZ unit specifications
2488M (electrical/optical): As per 2.5G unit and 2.5G/10G unit specifications
9953M (electrical/optical): As per 2.5G/10G unit specifications
Clock
Internal (accuracy: ±3.5 ppm, jitter unit not installed), Lock (2 MHz, 1.5 MHz, 64 kHz + 8 kHz, 2 Mbit/s, 1.5 Mbit/s),
external (ECL [AC] 50 , 9953M: 1.02 to 0.58 Vp-p, 50 ), received signal
Frame SDH/SONET, CID pattern, non-frame
Mapping See Fig. 1
Through Trance parent, over head overwrite, payload overwrite
PRBS: 2
11
1, 2
15
1, 2
20
1 (zero suppress, MP0122A/B installed), 2
20
1, 2
23
1, 2
31
1 (only concatenation mapping
Test patterns
16c/64c, conform to O.151)
Invert: On/off
Word: 16-bit programmable, all 0, all 1
Bit all (all, test pattern), FAS, B1, B2, B3, BIP-2, MS-REI, HP-REI, LP-REI
Timing: Single, single (burst) bit (1 to 64000), rate (1E3, 1E4, 1E5, 1E6, 1E7, 1E8, 1E9)
Error addition
User program AE-B [A: 1.0 to 9.9 (step: 0.1), B: 2 to 10]
Alternative: Error frame (0 to 8000), normal frame (1 to 8000)
LOS, LOF, MS-AIS, MS-RDI, AU-AIS, AU-LOP, HP-SLM, HP-TIM, HP-RDI, HP-UNEQ, TU-AIS, TU-LOP, TU-LOM, LP-SLM,
LP-TIM, LP-RDI, LP-UNEQ, LP-RFI
Alarm addition
Timing: Single, single (burst) frame
Alternative: Alarm frame (0 to 8000), normal frame (1 to 8000), all
Mode: Single, repeat, manual
In-service/Out-of-service
Errors: B1, B2, B3, BIP-2, MS-REI, HP-REI, LP-REI
Measurements Alarms: Power-fail, LOS, LOF, OOF, MS-AIS, MS-RDI, AU-AIS, AU-LOP, HP-SLM, HP-TIM, HP-RDI, HP-UNEQ, TU-AIS,
TU-LOP, TU-LOM, LP-SLM, LP-TIM, LP-RDI, LP-UNEQ, LP-RFI
Error performance: G.826, M2101, M2110, M2120
Preset: Alarm measurement condition
LEDs
LOS, LOF, OOF, MS-AIS, MS-RDI, AU-AIS, AU-LOP, HP-RDI, HP-SLM, TU-AIS, TU-LOM, TU-LOP, LP-RDI, LP-RFI, LP-SLM,
Tandem, sync. loss, errors
N1 byte (Type 1, Type 2), N2 byte
Tandem connection Errors: N2 BIP-2, TC-REI, OEI, IEC
Alarms: VC-AIS, ISF, FAS, HP-Incoming-AIS, HP-TC-RDI, HP-ODI, LP-Incoming-AIS, LP-TC-RDI, LP-ODI
Justification
AU pointer, TU pointer, C, C1/C2
Measurement: NDF, +PJC, PJC, Cons, C, C1/C2
Monitor SOH, POH, K1/K2, pointer, path trace (TIM alarms detectable), Tandem, payload
Signal of opposites polarity, regular with double, regular with missing, double of opposites polarity, 87-3/26-1 (normal, add, cancel),
Pointer sequence continuous pattern (normal, add, cancel), single pointer adjustment, maximum rate pointer burst, phase transient pointer burst,
initialize period polarity, cooldown period
Over head capture SOH/POH (any 1 byte), H1/H2, K1/K2
Dummy channel setting
Payload: Dummy, copy, mixed payload
Setting: POH, pathtrace, SS bit, Tandem
Simultaneous measurement
VC2, VC12, VC11
Trouble search Auto search for errors/alarms in all measured channels
Measurement period: 0.5, 1, 2, 5, 10 s
Delay Measurement range: 0 to 999 µs, 1.0 to 999.9 ms, 1.0 to 10.0 s, time out
Display accuracy: ±5 µs (0.5, 1 s), ±50 µs (2, 5, 10 s)
Switching time measurement
Measurement range: 1 to 2000 ms, >2000 ms
Trigger
Internal: B1, B2, B3, BIP-2, MS-REI, HP-REI, LP-REI, MS-AIS, AU-AIS, AU-LOP, HP-RDI, TU-AIS, TU-LOM, TU-LOP, LP-RDI,
APS (K1/K2) LP-RFI, Bit
External: Measures trigger input signal (active high)
Threshold: Specify non-error alarm between 1 ms, 10 ms, 100 ms
Sequence generation: 2 to 64 word, repeat (8000 frame)
Sequence capture: 2 to 64 word, repeat (8000 frame)
Frequency measurement
Range: ±100 ppm, Accuracy: ±3.5 ppm (jitter unit not installed)
OH change: SOH/POH 1 byte, K1/K2, RSOH, MSOH, SOH, POH (except B1, B2, B3, BIP-2)
PTR 64 frame: AU pointer, TU pointer
Timing: Single, repeat (2 to 64)
Over head test Setting: PTR, NDF, +PJC, PJC
OH BERT: SOH/POH 1 byte (exclude B1, B2, B3, BIP-2), D1-D3, D4-D12
Test pattern: 2
11
1, 2
15
1
OH add/drop: SOH/POH 1 byte, D1-D3, D4-D12 (exclude B1, B2, B3, BIP-2 additional type)
Japan mapping (option 09)
VC11 Signaling (8-multiframe, 64-multiframe setting)
Frame memory/capture
Memory size: 64 frame (156M, 622M, Option 13), 64 frame (MU150008A-01/150009A-01/150010A-01, 2.5G),
26 frame (MU150000A-01, 2.5G/10G)
Insert/extract Bit rate: 10G (52M, 156M), 2.5G (52M, 156M)
Payload offset ±100 ppm/0.1 ppm step
Auxiliary interface Clock sync output, trigger input, trigger output, DCC interface (V.11), orderwire, receive clock output
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