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DIGITAL LINK MEASURING INSTRUMENTS
2
Specifications
Internal
Operating frequency: 10 kHz to 200 MHz (accuracy: ±2 ppm)
Resolution: 1 kHz steps (>1 to 200 MHz), 100 Hz steps (10 kHz to 1 MHz)
External
Clock Input frequency range: 10 kHz to 200 MHz
Input level: AC, 0.5 to 2.0 Vp-p (50 Ω), BNC connector
External (at locked)
Input frequency range: 10 MHz ±100 ppm, 64 kHz ±100 ppm
Input level: AC, 0.5 to 2.0 Vp-p (50 Ω), BNC connector
External modulation input
Modulation frequency range: 10 Hz to 1.3 MHz
Input level range (sine wave): –1 to +1 V (75 Ω), BNC connector
Reference output (jitter-free output): AC, 1 Vp-p (50 Ω), SMA
Jitter: 0 to 50.5 UIp-p (clock frequency: >100 to 200 MHz)
∗Switchable to 50 UI/2 UI range
Jitter modulation function
(option)
PRBS Pattern: 2
n
– 1 (n: 7, 9, 11, 15, 20, 23, 31), variable mark ratio, logic selectable
Zero substitution pattern: 2
n
(n: 7, 9, 11, 15); pattern length: n to 2
n
– 1, logic selectable
PRGM pattern: 2 to 65,536 bits/channel bit length, logic selectable
Mixed pattern: Mixed PRGM and PRBS pattern, logic selectable
∗Block numbers: 2 to 32 [PRGM bit length/block: 8 to 8,912 bits; PRBS bit length/block: 8 to 131,072 bits
Test pattern (pulse pattern (depend on block numbers)]
generator, error detector) PON pattern [TDMA test patterns with preamble inserted in ahead of Mixed patterns (PRGM and PRBS)]
Preamble (1010...): 0 to 64 bits; guard time: –2,097,083 to 2,097,067 bits (1 bit resolution)
Burst mode: Internal (burst cycle: 0.1 to 10 ms), external (enable length: 8 to 2,097,144 bits)
Pattern edit function
Edit mode: Dump, timing diagram, state table
Edit results storage: Internal HDD or FDD
Each channel, simultaneous or independently
Error type: Normal, burst
Normal mode (internal: cyclic or single, external)
Error rate: 10
–n
(n: 3 to 9)
Error insertion
Insert area: Entire area, selected blocks (in Mixed pattern or PON pattern)
Burst mode (internal/external)
Error rate: 10
–n
(n: 2 to 9)
Internal enable length: 20 to 140 ms (resolution: 20 ms)
Internal cycle: 1 to 10 s (resolution: 1 s)
External mode: Error of specified rate inserted in external signal enable period
Output No.: 16 (multipin connector), output on/off and logic selectable
Output waveform: NRZ (data), RZ (clock)
Output level: ECL, PECL, TTL, LVTTL, VAR
VAR range
Data/clock output Amplitude: 0.5 to 5 V (10 mV steps, high impedance), 0.25 to 2.5 V (5 mV steps, 50 Ω)
Offset: –4.5 to + 5 V (5 mV steps, high impedance), –2.25 to + 2.5 V (2.5 mV steps, 50 Ω)
Rise/fall times (typ.): 1.3 ns (1 Vp-p, 50 Ω termination)
Clock delay: –5 to +5 ns (100 ps steps)
Data skew: –5 to +5 ns (100 ps steps)
Input No.: 16, logic selectable, multipin connector
Input waveform: NRZ (data), RZ (clock)
Input level: ECL, PECL, TTL, LVTTL, VAR
Data/clock input VAR input range
Amplitude: 0.5 to 5 V (50 Ω)
Threshold level: –5 to + 5 V (5 mV steps, in 50 Ω to GND termination)
Clock delay: –5 to +5 ns (100 ps steps)
Channel No.: 16 channels simultaneous measurement (selectable measurement channels)
Measurement data
Signal format: Continuous or burst (internal/external)
Error detection: All, insertion, omission
Measurement region: All, PRGM, PRBS selectable, and each block selectable with block configuration
Display
Error rate: 0 x 10
–16
to 1.0000 x 10
0
Bit error measurement Error count: 0 to 9999999, 1.0000 x 10
7
to 9.9999 x 10
16
Error interval: 0 to 9999999, 1.0000 x 10
7
to 9.9999 x 10
16
Error free interval: 0.0000 to 100.0000%
Error performance: ITU-T Rec. G.821
Measurement mode: Single, repeat, untimed (1 second to 99 days 23 hours 59 minutes 59 seconds)
Auto sync: ON/OFF switchable [threshold value: 1 x 10
–n
(n: 2 to 8)], with autosearch function
Alarm measurement Detected items: Power loss, clock loss, pattern sync loss (PRGM, PRBS)
Continued on next page
[UIp-p]
50.5
50
2.02
2
0.404
0.2
STM-1 (example)
50 UI range
2 UI range
Jitter amplitude
Modulation frequency
0.01 0.1 0.5 2.6 6.5 65 260 1300 [kHz]
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